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| Rail-to-Rail, Fast, Low Power 2.5 V to 5.5 V, Single-Supply TTL/CMOS Comparator ADCMP608 FEATURES Fully specified rail to rail at VCC = 2.5 V to 5.5 V Input common-mode voltage from -0.2 V to VCC + 0.2 V Low glitch CMOS-/TTL-compatible output stage 40 ns propagation delay Low power: 1 mW at 2.5 V Shutdown pin Power supply rejection > 60 dB -40C to +125C operation FUNCTIONAL BLOCK DIAGRAM NONINVERTING INPUT + ADCMP608 INVERTING INPUT - Q OUTPUT SDN APPLICATIONS High speed instrumentation Clock and data signal restoration Logic level shifting or translation High speed line receivers Threshold detection Peak and zero-crossing detectors High speed trigger circuitry Pulse-width modulators Current-/voltage-controlled oscillators Figure 1. GENERAL DESCRIPTION The ADCMP608 is a fast comparator fabricated on XFCB2, an Analog Devices, Inc. proprietary process. This comparator is exceptionally versatile and easy to use. Features include an input range from VEE - 0.2 V to VCC + 0.2 V, low noise, TTL-/CMOScompatible output drivers, and shutdown inputs. The device offers 40 ns propagation delays driving a 15 pF load with 10 mV overdrive on 500 A typical supply current. A flexible power supply scheme allows the device to operate with a single +2.5 V positive supply and a -0.2 V to + 2.7 V input signal range up to a +5.5 V positive supply with a -0.2 V to +5.7 V input signal range. The TTL-/CMOS-compatible output stage is designed to drive up to 15 pF with full rated timing specifications and to degrade in a graceful and linear fashion as additional capacitance is added. The input stage of the comparator offers robust protection against large input overdrive, and the outputs do not phase reverse when the valid input signal range is exceeded. The ADCMP608 is available in a tiny 6-lead SC70 package with a single-ended output and a shutdown pin. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2007 Analog Devices, Inc. All rights reserved. 06769-001 ADCMP608 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Electrical Characteristics............................................................. 3 Absolute Maximum Ratings............................................................ 4 Thermal Resistance ...................................................................... 4 ESD Caution.................................................................................. 4 Pin Configuration and Function Descriptions............................. 5 Typical Performance Characteristics ............................................. 6 Application Information...................................................................7 Power/Ground Layout and Bypassing........................................7 TTL-/CMOS-Compatible Output Stage ....................................7 Optimizing Performance..............................................................7 Comparator Propagation Delay Dispersion ..............................7 Crossover Bias Point .....................................................................8 Minimum Input Slew Rate Requirement ...................................8 Typical Application Circuits ............................................................9 Outline Dimensions ....................................................................... 10 Ordering Guide .......................................................................... 10 REVISION HISTORY 4/07--Revision 0: Initial Version Rev. 0 | Page 2 of 12 ADCMP608 SPECIFICATIONS ELECTRICAL CHARACTERISTICS VCC = 2.5 V, TA = -40C to +125C. Typical values are TA = 25C, unless otherwise noted. Table 1. Parameter DC INPUT CHARACTERISTICS Voltage Range Common-Mode Range Differential Voltage Offset Voltage Bias Current Offset Current Capacitance Resistance, Differential Mode Resistance, Common Mode Active Gain Common-Mode Rejection SHUTDOWN PIN CHARACTERISTICS 1 VIH VIL IIH Sleep Time Wake-Up Time DC OUTPUT CHARACTERISTICS Output Voltage High Level Output Voltage Low Level AC PERFORMANCE 2 Rise Time/Fall Time Propagation Delay Propagation Delay Skew--Rising to Falling Transition Overdrive Dispersion Common-Mode Dispersion POWER SUPPLY Supply Voltage Range Positive Supply Current Power Dissipation Power Supply Rejection Ratio Shutdown Current 1 Symbol VP, VN Conditions VCC = 2.5 V to 5.5 V VCC = 2.5 V to 5.5 V VCC = 2.5 V to 5.5 V Min -0.2 -0.2 -5.0 -0.4 -1.0 Typ Max VCC VCC VCC +5.0 +0.4 +1.0 7000 4000 Unit V V V mV A A pF k k dB dB dB V V A ns ns V V ns ns ns ns ns ns ns ns VOS IP, IN CP, CN -0.5 V to VCC + 0.5 V -0.5 V to VCC + 0.5 V AV CMRR VCC = 2.5 V, VCM = -0.2 V to 2.7 V VCC = 5.5 V Comparator is operating Shutdown guaranteed VIH = VCC lCC < 100 A VPP = 10 mV, output valid VCC = 2.5 V to 5.5 V IOH = 0.8 mA, VCC = 2.5 V IOL = 0.8 mA, VCC = 2.5 V VCC = 2.5 V to 5.5 V 10% to 90%, VCC = 2.5 V 10% to 90%, VCC = 5.5 V VOD = 10 mV, VCC = 2.5 V VOD = 50 mV, VCC = 5.5 V VCC = 2.5 V VCC = 5.5 V 10 mV < VOD < 125 mV -0.2 V < VCM < VCC + 0.2 V 3 1 200 100 80 45 45 2.0 -0.2 -6 VCC +0.4 +6 +0.4 300 150 tSD tH VOH VOL tR, tF tPD VCC - 0.4 0.4 25 to 50 45 to 75 30 to 50 35 to 60 4.5 8 12 1.5 2.5 5.5 800 1300 2.0 7.15 350 VCC IVCC PD PSRR ISD VCC = 2.5 V VCC = 5.5 V VCC = 2.5 V VCC = 5.5 V VCC = 2.5 V to 5.5 V VCC = 2.5 V to 5.5 V 550 800 1.375 4.95 -50 250 V A A mW mW dB A The output will be in a high impedance mode when the device is in shutdown mode. Note that this feature should be used with care since the enable/disable time is much longer than with a true tristate output. 2 VIN = 100 mV square input at 1 MHz, VCM = 0 V, CL = 15 pF, VCCI = 2.5 V, unless otherwise noted. Rev. 0 | Page 3 of 12 ADCMP608 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Supply Voltages Supply Voltage (VCC to GND) Supply Differential Input Voltages Input Voltage Differential Input Voltage Maximum Input/Output Current Shutdown Control Pin Applied Voltage (SDN to GND) Maximum Input/Output Current Output Current Temperature Operating Temperature, Ambient Operating Temperature, Junction Rating -0.5 V to +6.0 V -6.0 V to +6.0 V -0.5 V to VCC+ 0.5 V (VCC + 0.5 V) 50 mA -0.5 V to VCC + 0.5 V 50 mA 50 mA -40C to +125C 150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE JA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 3. Thermal Resistance Package Type ADCMP608 6-Lead SC70 1 JA1 426 Unit C/W Measurement in still air. ESD CAUTION Rev. 0 | Page 4 of 12 ADCMP608 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Q1 6 VCC SDN VN 06769-002 ADCMP608 VEE 2 VP 3 TOP VIEW (Not to Scale) 5 4 Figure 2. Pin Configuration Table 4. ADCMP608 Pin Function Descriptions Pin No. 1 2 3 4 5 6 Mnemonic Q VEE VP VN SDN VCC Description Noninverting Output. Q is at logic high if the analog voltage at the noninverting input, VP, is greater than the analog voltage at the inverting input, VN. Negative Supply Voltage. Noninverting Analog Input. Inverting Analog Input. Shutdown. Drive this pin low to shut down the device. VCC Supply. Rev. 0 | Page 5 of 12 ADCMP608 TYPICAL PERFORMANCE CHARACTERISTICS VCC =2.5 V, TA = 25C, unless otherwise noted. 5 4 PROPAGATION DELAY (ns) 38.0 37.8 37.6 37.4 37.2 37.0 36.8 36.6 36.4 06769-003 3 2 1 PROPAGATION DELAY FALL IB (A) 0 -1 -2 -3 -4 -5 -1.0 +125C +25C -40C -0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 PROPAGATION DELAY RISE 36.2 36.0 0.5 1.0 1.5 2.0 2.5 3.5 3.0 VCM AT VCC (2.5V) VCM AT VCC (2.5V) Figure 3. Input Bias Current vs. Input Common-Mode Voltage Figure 6. Propagation Delay vs. Input Common-Mode Voltage 60 55 50 45 TPD (ns) Q 40 35 30 25 20 VCC = 2.5V RISE DELAY 0 50 VCC = 5.5V RISE DELAY VCC = 5.5V FALL DELAY VCC = 2.5V FALL DELAY 06769-004 0.5V/DIV 10ns/DIV 100 OD (mV) 150 Figure 4. Propagation Delay vs. Input Overdrive at VCC = 2.5 V and 5.5 V Figure 7. 1 MHz Output Voltage Waveform VCC = 2.5 V 1.5 SOURCE 1.0 SINK Q LOAD CURRENT (mA) 0.5 0 -0.5 06769-005 06769-008 -1.0 -1.0 -0.5 1V/DIV 10ns/DIV 0 0.5 1.0 1.5 VOUT (V) 2.0 2.5 3.0 3.5 4.0 Figure 5. Load Current (mA) vs. VOH/VOL Figure 8. 1 MHz Output Voltage Waveform VCC = 5.5 V Rev. 0 | Page 6 of 12 06769-007 06769-006 ADCMP608 APPLICATION INFORMATION POWER/GROUND LAYOUT AND BYPASSING The ADCMP608 comparator is a high speed device. Despite the low noise output stage, it is essential to use proper high speed design techniques to achieve the specified performance. Because comparators are uncompensated amplifiers, feedback in any phase relationship is likely to cause oscillations or undesired hysteresis. Of critical importance is the use of low impedance supply planes, particularly the output supply plane (VCC) and the ground plane (GND). Individual supply planes are recommended as part of a multilayer board. Providing the lowest inductance return path for switching currents ensures the best possible performance in the target application. It is also important to adequately bypass the input and output supplies. A 0.1 F bypass capacitor should be placed as close as possible to the VCC supply pin. The capacitor should be connected to the GND plane with redundant vias placed to provide a physically short return path for output currents flowing back from ground to the VCC pin. High frequency bypass capacitors should be carefully selected for minimum inductance and ESR. Parasitic layout inductance should also be strictly controlled to maximize the effectiveness of the bypass at high frequencies. A1 VLOGIC Q1 +IN -IN AV OUTPUT A2 Q2 06769-009 GAIN STAGE OUTPUT STAGE Figure 9. Simplified Schematic Diagram of TTL-/CMOS-Compatible Output Stage OPTIMIZING PERFORMANCE As with any high speed comparator, proper design and layout techniques are essential for obtaining the specified performance. Stray capacitance, inductance, common power and ground impedances, or other layout issues can severely limit performance and can often cause oscillation. The source impedance should be minimized as much as is practicable. High source impedance, in combination with the parasitic input capacitance of the comparator, causes an undesirable degradation in bandwidth at the input, thus degrading the overall response. Higher impedances encourage undesired coupling. TTL-/CMOS-COMPATIBLE OUTPUT STAGE Specified propagation delay performance can be achieved only by keeping the capacitive load at or below the specified minimums. The output of the ADCMP608 is designed to directly drive one Schottky TTL, or three low power Schottky TTL loads, or the equivalent. For large fan outs, buses, or transmission lines, use an appropriate buffer to maintain the excellent speed and stability of the comparator. With the rated 15 pF load capacitance applied, more than half of the total device propagation delay is output stage slew time. Because of this, the total propagation delay decreases as VCC decreases, and instability in the power supply may appear as excess delay dispersion. Delay is measured to the 50% point for whatever supply is in use; thus, the fastest times are observed with the VCC supply at 2.5 V, and larger values are observed when driving loads that switch at other levels. Overdrive and input slew rate dispersions are not significantly affected by output loading and VCC variations. The TTL-/CMOS-compatible output stage is shown in the simplified schematic diagram (see Figure 9). Because of its inherent symmetry and generally good behavior, this output stage is readily adaptable for driving various filters and other unusual loads. COMPARATOR PROPAGATION DELAY DISPERSION The ADCMP608 comparator is designed to reduce propagation delay dispersion over a wide input overdrive range of 10 mV to VCC - 1 V. Propagation delay dispersion is the variation in propagation delay that results from a change in the degree of overdrive or slew rate (how far or how fast the input signal exceeds the switching threshold). Propagation delay dispersion is a specification that becomes important in high speed, time-critical applications, such as data communication, automatic test and measurement, and instrumentation. It is also important in event-driven applications, such as pulse spectroscopy, nuclear instrumentation, and medical imaging. Dispersion is defined as the variation in propagation delay as the input overdrive conditions are changed (Figure 10 and Figure 11). ADCMP608 dispersion is typically < 12 ns as the overdrive varies from 10 mV to 125 mV. This specification applies to both positive and negative signals because the device has very closely matched delays for both positive-going and negativegoing inputs, and very low output skews. Remember to add the actual device offset to the overdrive for repeatable dispersion measurements. Rev. 0 | Page 7 of 12 ADCMP608 500mV OVERDRIVE CROSSOVER BIAS POINT Rail-to-rail inputs of this type, in both op amps and comparators, have a dual front-end design. Certain devices are active near the VCC rail and others are active near the VEE rail. At some predetermined point in the common-mode range, a crossover occurs. At this point, normally VCC/2, the direction of the bias current reverses and there are changes in measured offset voltages and currents. 06769-010 INPUT VOLTAGE 10mV OVERDRIVE VN VOS DISPERSION Q OUTPUT Figure 10. Propagation Delay--Overdrive Dispersion The ADCMP608 slightly elaborates on this scheme. Crossover points can be found at approximately 0.8 V and 1.6 V. MINIMUM INPUT SLEW RATE REQUIREMENT INPUT VOLTAGE 1V/ns VN VOS 10V/ns Q OUTPUT Figure 11. Propagation Delay--Slew Rate Dispersion 06769-011 DISPERSION With the rated load capacitance and normal good PC board design practice, as discussed in the Optimizing Performance section, these comparators should be stable at any input slew rate with no hysteresis. Broadband noise from the input stage is observed in place of the violent chattering seen with most other high speed comparators. With additional capacitive loading or poor bypassing, oscillation may be encountered. These oscillations are due to the high gain bandwidth of the comparator in combination with feedback through parasitics in the package and PC board. In many applications, chattering is not harmful. Rev. 0 | Page 8 of 12 ADCMP608 TYPICAL APPLICATION CIRCUITS 2.5V TO 5V 0.1F INPUT 2k 2k ADCMP608 OUTPUT 06769-012 0.1F Figure 12. Self-Biased, 50% Slicer CMOS VCC 2.5V TO 5V LVDS 100 ADCMP608 OUTPUT 06769-013 Figure 13. LVDS-to-CMOS Receiver Rev. 0 | Page 9 of 12 ADCMP608 OUTLINE DIMENSIONS 2.20 2.00 1.80 2.40 2.10 1.80 1.35 1.25 1.15 PIN 1 1.30 BSC 1.00 0.90 0.70 6 1 5 2 4 3 0.65 BSC 1.10 0.80 0.40 0.10 0.46 0.36 0.26 0.10 MAX 0.30 0.15 0.10 COPLANARITY SEATING PLANE 0.22 0.08 COMPLIANT TO JEDEC STANDARDS MO-203-AB Figure 14. 6-Lead Thin Shrink Small Outline Transistor Package (SC70) (KS-6) Dimensions shown in millimeters ORDERING GUIDE Model ADCMP608BKSZ-R2 1 ADCMP608BKSZ-RL1 ADCMP608BKSZ-REEL71 1 Temperature Range -40C to +125C -40C to +125C -40C to +125C Package Description 6-Lead Thin Shrink Small Outline Transistor Package (SC70) 6-Lead Thin Shrink Small Outline Transistor Package (SC70) 6-Lead Thin Shrink Small Outline Transistor Package (SC70) Package Option KS-6 KS-6 KS-6 Branding G0U G0U G0U Z = RoHS Compliant Part. Rev. 0 | Page 10 of 12 ADCMP608 NOTES Rev. 0 | Page 11 of 12 ADCMP608 NOTES (c)2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06769-0-4/07(0) Rev. 0 | Page 12 of 12 |
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